The present invention relates to lead-frame-based semiconductor packages, and more particularly, to a semiconductor package with a lead frame as a chip carrier for accommodating a multi-media card (MMC) chip, and a fabrication method of the semiconductor package.
Multi-media cards (MMC) are small-scale integrated circuit (IC) devices having control and memory chips for storing and processing digital video and audio data. Conventionally, MMC chips are packaged and accommodated on a chip carrier such as substrate or tape; however, this substrate-based or tape-based packaging technology is relatively cost-ineffective to implement.
Therefore, Taiwan Publication No. 484222 teaches a lead-frame-based semiconductor package in which a lead frame is employed as a chip carrier for MMC chips. As shown in FIG. 4, this semiconductor package 1 is provided with a lead frame 10 having a plurality of leads 11. Each of the leads 11 is defined with an inner lead portion 110, a middle lead portion 111 and an outer lead portion 112, wherein the middle lead portion 111 interconnects the inner and outer lead portions 110, 112. The inner lead portion 110 is used for chip-mounting purpose, and lower in elevation than the outer lead portion 112 by a predetermined height difference.
A chip 12, such as a MMC chip, is mounted on the inner lead portions 110, and electrically connected to the leads 11 by a plurality of bonding wires 13. Then, an encapsulant 14 is formed to encapsulate the leads 11, chip 12 and bonding wires 13, wherein the outer lead portions 112 are exposed to outside of the encapsulant 14 for mediating electrical connection between the semiconductor package 1 and an external device such as a printed circuit board (not shown). These components encapsulated by the encapsulant 14 can thus be protected against external moisture, contaminants and impact.
However, the above semiconductor package 1 has significant drawbacks. One is difficulty in obtaining desirable planarity of the leads; when the leads 11 are shaped or deformed to form inner lead portions 110, middle lead portions 111 and outer lead portions 112, it may easily lead to poor planarity of the outer lead portions 112, or a R angle (as circled in FIG. 4) at an interconnecting portion between an outer lead portion 112 and a corresponding middle lead portion 111. As such, during a molding process, a resin compound such as epoxy resin used for forming the encapsulant 14 may flash over the outer lead portions 112 that are to be exposed to outside of the encapsulant 14, thereby adversely affecting reliability and quality of electrical connection between the semiconductor package 1 and the external device.
A primary objective of the present invention is to provide a lead-frame-based semiconductor package and a fabrication method thereof, which can effectively maintain planarity of a lead frame or leads, and prevent resin flash during a molding process, so as to assure reliability and quality of electrical connection for fabricated package products.
In accordance with the above and other objectives, the present invention proposes a lead-frame-based semiconductor package, comprising: a lead frame having a plurality of first leads and second leads, each lead having an upper surface and a lower surface opposed to the upper surface, wherein each of the first leads is formed with an extending portion smaller in thickness than the corresponding one of the first leads in a manner that, an upper surface of the extending portion is flush with the upper surface of the corresponding first lead, and a lower surface of the extending portion forms a predetermined height difference with respect to the lower surface of the corresponding first lead; at least a chip mounted over the upper surfaces of the extending portions; a plurality of bonding wires for electrically connecting the chip to the first and second leads; an encapsulant for encapsulating the upper surfaces of the first and second leads, the upper surfaces of the extending portions, the chip and the bonding wires; and a non-conductive material applied over the lower surfaces of the extending portions, wherein the lower surfaces of the first and second leads are exposed to outside of the non-conductive material. The exposed lower surfaces of the first and second leads are used to mediate electrical connection between the semiconductor package and an external device such as a printed circuit board. The non-conductive material may be the same as or different from a resin material used for forming the encapsulant.
In one embodiment, the first leads of the lead frame are formed with the extending portions respectively; a molding process is performed to form an encapsulant for encapsulating the first and second leads, extending portions, chip and bonding wires, allowing the lower surfaces of the first and second leads and the lower surfaces of the extending portions to be exposed to outside of the encapsulant. Then, a grind process is performed to grind the exposed lower surfaces of the extending portions so as to allow the extending portions to be smaller in thickness than the first leads, wherein the lower surfaces of the extending portions form a predetermined height different with respect to the lower surfaces of the first leads. Thereafter, a non-conductive material is applied over the lower surfaces of the extending portions; an applied thickness of the non-conductive material is equal to the predetermined height different between the lower surfaces of the extending portions and the lower surfaces of the first leads, so as to allow an exposed surface of the non-conductive material to be flush with the lower surfaces of the first leads.
In another embodiment, the extending portions formed at the first leads of the lead frame are subject to a half-etching process for etching the lower surfaces of the extending portion, so as to allow the extending portions to be smaller in thickness than the first leads. Then, an encapsulant is formed to encapsulate the first and second leads, extending portions, chip and bonding wires, allowing the lower surfaces of the first and second leads to be exposed to outside of the encapsulant.
The exposed lower surfaces of the first and second leads may be plated with gold for mediating mediate electrical connection between the semiconductor package and the external printed circuit board.
The above package fabrication method can effectively maintain planarity of the lead frame or leads, and prevent the resin material for forming the encapsulant from flashing over the exposed surfaces of the leads, thereby assuring reliability and quality of electrical connection for fabricated package products.